1. Field of the Invention
This invention relates to a method of fabrication of semiconductor devices, and more particularly, to a method of providing extra metal routing in a gate portion of semiconductor devices.
2. Description of the Related Art
Combining both embedded DRAM memory and other components, such as high speed logic circuits, onto a single chip is often useful. In many embodiments, the DRAM memory components are fabricated in a central array portion of a semiconductor device while the logic circuits are fabricated in periphery portions of the semiconductor device. In some embodiments, faster speed is achieved, and bandwidth and capacitance problems are reduced when incorporating both memory and logic components on a single memory device, or chip.
In a typical memory device having both memory (array components) and logic (periphery components), the memory device often includes one or more local interconnects formed above the memory or logic components. The local interconnect may include metal routing between components of the memory device, either in the array or the periphery. Above the local interconnects, additional layers containing additional circuitry, such as logic components, memory contacts, or metal routing, may be formed. In some embodiments, a metal layer above the local interconnects comprises many of the metal routings used by the memory device.
As the density of components on a single memory device increases, the metal routing in the metal layer of the memory device also becomes increasingly dense and difficult to fabricate. Accordingly, there is an increasing need for systems and methods of incorporating additional routing in a memory device without increasing the size of the memory device.